Link aggregators provide automatic digital multiplexing and de-multiplexing for aggregating both transmit and receive data transfer for a number of low-speed channel sources using a single or a small number of high-speed channels. Such data aggregators can be used to reduce the number of physical links required for a specified data throughput by multiplexing multiple low-speed serial links into higher-rate serial links, where certain link aggregators allow independent operation of low-speed channels or lanes at different data transfer rates or speeds. Transmit data paths and link aggregators can include encoding as well as scrambling circuitry, with the data scrambling typically following interleaving/multiplexing circuitry. Receive data paths may similarly include decoding as well as descrambling circuitry, commonly provided prior to de-multiplexing. A typical configuration includes a pair of link aggregators at opposite ends of a high-speed transmission medium, each having local connections to low-speed data sources/consumers, with the link aggregators and intervening high-speed communications channel(s) facilitating point-to-point bidirectional communications using fewer end-to-end physical links without sacrificing overall throughput.
Digital data scrambling and descrambling ideally provides a relatively high degree of randomness in the data flowing in the high-speed transmission medium, thereby mitigating or avoiding long sequences of bits of the same value, wherein scrambling can be viewed as a randomizing operation. Data scrambling provides significant advantages in certain applications, including improved clock recovery capabilities and reduced interference. For instance, improper scrambling (or no scrambling) may render the high-speed data transmitted between link aggregators highly input data dependent, with the possibility of including long sequences of identical bits. This condition makes it more difficult for clock recovery circuitry, automatic gain control (AGC) and other adaptive circuits of a receiver to function properly. Also, improper or insufficient scrambling (i.e., insufficient randomization) may result in highly data-dependent transmission power spectrum, thereby increasing the likelihood of exceeding maximum power spectral density requirements of a given transition medium, and increased likelihood of channel-channel interference.
Scrambling and descrambling ideally results in pseudo-random modification of the values of some bits in a data stream, where the type of scrambling and descrambling can be characterized in terms of a polynomial generating a specific pseudorandom bit sequence (PRBS). Different communications interface standards, however, utilize different polynomials. For example, fixed packet size scramblers using 8b/10b encoding for Synchronous Optical Networking (SONET) operate according to a scrambler polynomial X7+X+1, whereas other communications standards employ different polynomials. Furthermore, encoding techniques employed in link aggregators may exacerbate the lack of randomness in transmitted data. For example, 8b/10b encoding may result in high dependency on input data characteristics, where constant 8-bit raw data translates to 10-bit constant data, thereby negatively impacting clock data recovery (CDR), interference, and other performance metrics in various applications such as Gigabit Ethernet, XAUI, CPPRI, PCI Express, USB3.0, IEEE1394, Serial ATA, Serial Attached SCSI (SAS), Fibre Channel, Serial Storage Architecture (SSA), InfiniBand, Serial RapidIO, DVB ASI, DisplayPort Main Link, DVE and HDMI, HyperTransporet, and CoaXPress. Consequently, improved link aggregators and scrambling/descrambling apparatus and techniques are desirable to facilitate highly random high-speed data transmission for use in association with a variety of different scrambler/descrambler polynomials.